Low drop-out (LDO) type linear voltage regulators are used in a variety of applications. In particular, these regulators may be used in mobile telephones to deliver a regulated voltage from a battery power supply voltage to radio transmitter and receiver circuits.
By way of example, a standard linear regulator 100 is illustrated in FIG. 1. An output of the regulator 100 delivers a regulated voltage VOUT to a load Z (not shown). The load Z represents, for example, radio circuits present in a mobile telephone. The regulator 100 is powered by a voltage VIN delivered by a battery or other supply source. The regulator 100 comprises a differential amplifier 110 whose output drives the gate of a P-channel metal oxide semiconductor (PMOS) transistor Q1 having a threshold voltage VTP. The output stage of the amplifier 110 has an output resistance Ro that determines the gain of the amplifier 110 and the maximum current that it can deliver at its output.
The transistor Q1 receives the voltage VIN at its input terminal (source). Its output terminal (drain) is connected to node 120, which is the output of the regulator 100. Node 120 also is connected to the anode of a capacitor CBYP (having parasitic resistance RESR) for filtering and stabilizing the voltage VOUT. Capacitor CBYP (with parasitic resistance RESR) is parallel-connected with the load Z. The amplifier 110 receives a reference voltage VREF at its inverting input and a feedback voltage VFB at its non-inverting input. The voltage VFB is, for example, a fraction of the voltage VOUT provided to the input of the amplifier 110 by a divider bridge including two resistors R2, R1.
Operation of a regulator of this kind, which is well known to those skilled in the art, includes modulating the control voltage (gate voltage Vg) of the transistor Q1 using the amplifier 110. This is done as a function of the difference between the voltage VFB and the reference voltage VREF. When the voltage Vg is substantially smaller than VIN−VTP, the transistor Q1 is on because its gate-source voltage Vgs is substantially higher than the threshold voltage VTP. When the voltage Vg is higher than VIN−VTP, the transistor Q1 is off. In a stabilized state, the voltage VOUT is regulated in the neighborhood of its nominal valve VOUT,NOM, which is equal to [(R2+R1) VREF/R1].
The conventional regulator 100 of FIG. 1, however, suffers from an undesirable overshoot phenomenon for two main reasons. First, in an application such as supplying a regulated supply to radio circuits of a mobile telephone, it is important that the amplifier 110 consume as little power as possible to maintain the charge stored in the battery. To this end, the bias current of the amplifier should be as low as possible, limiting the speed and bandwidth of the amplifier. Second, the regulation transistor Q1 must have a low series resistance RdsON in the “on” state (drain-source resistance) so that it can deliver high current without any prohibitive voltage dropout at its terminals. Thus, the transistor Q1 conventionally has a high gate width-to-length ratio. Due to its size and its high W/L ratio, the transistor Q1 also has a high gate capacitance Cg (not shown) between gate and drain. The combination of these two factors tends to make the LDO regulator slow to respond to transients.
While these various characteristics are desirable to obtain a regulator with low power consumption and low voltage dropout, driving a regulation transistor that has high gate capacitance Cg with an amplifier with a limited maximum output current causes an undesirable overshooting phenomena, in certain conditions, at the output of the regulator. For example, during startup, the bandwidth of the regulator can be too low to sufficiently stop high-current startup transients (300-400 mAmps or more) from creating voltage overshoot at the output of the regulator. A target voltage of 1.8 V, for example, can be overshot by as much as 100-200 mV. Large overshoot voltages such as these can take a long time to settle, because most conventional regulators are designed without a large current sink capability. As a result, when load currents are light, the output voltage overshoot can overstress the integrated circuit components supplied by the regulator for extended periods of time. Since these devices are often implemented in low voltage processes, these sensitive devices can be overstressed for significant periods of time by the overshoot voltage and potentially be permanently damaged. The overshoot can also force these sensitive circuits outside their simulated and guaranteed operating ranges, causing errors in device operation to occur.